By Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel (auth.)

This publication indicates readers the right way to boost energy-efficient algorithms and architectures to let high-definition 3D video coding on resource-constrained embedded units. clients of the Multiview Video Coding (MVC) typical face the problem of exploiting its 3D video-specific coding instruments for expanding compression potency on the fee of accelerating computational complexity and, hence, the power intake. This publication permits readers to minimize the multiview video coding power intake via together contemplating the algorithmic and architectural degrees. assurance contains an advent to 3D video clips and an intensive dialogue of the present state of the art of 3D video coding, in addition to energy-efficient algorithms for 3D video coding and energy-efficient structure for 3D video coding.

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Additional info for 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures

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Still, the current lack of MVC-oriented ASIC optimizations prohibits further increase in both performance and energy efficiency. On the other hand, multimedia processors/DSPs allow high flexibility to multiple standards while providing reduced performance and poor energy efficiency if compared to ASICs. Additionally, reconfigurable processors may allow significant increase in performance and flexibility through instruction set architecture (ISA) extensions. The reconfigurable processors, however, present reconfiguration energy issues and are unable to reach the ASIC-like performance and energy efficiency required by the 3D multimedia applications.

The algorithm that exploits these inter-frame similarities is the motion estimation (ME). 14), the region that represents the best match for the current block or macroblock. 14, is generated. 13), there is no motion between T0 and T1, so the motion vector m2 is probably zero. The dancers moving (woman’s face in the yellow box) present a displacement along the time; this displacement is represented by m1. The set of motion vectors of a given frame are called motion field and represent valuable information to understand the motion of an object as time progresses.

Berekovic et al. 264/AVC to the ADRES (coarse-grain reconfigurable processor) delivering throughput for real-time CIF decoding at 50 MHz with a 4 × 4-core array. CRISP, a coarse grain reconfigurable stream processor (Chen and Chien 2008), implements an image processing pipeline reaching 55 fps for HD1080p resolution. Aggressive performance losses are expected for video coding due to increased complexity compared to the implemented image processing algorithms. In Bauer et al. (2007), the rotating instruction set processing platform (RISPP) is presented bringing more flexibility to extensible processors.

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